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MC100LVEL30DWR2G Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100LVEL30DWR2G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 6 page © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 7 1 Publication Order Number: MC100LVEL30/D MC100LVEL30 3.3VECL Triple D Flip−Flop with Set and Reset Description The MC100LVEL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip−flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs. Features • 1200 MHz Minimum Toggle Frequency • 450 ps Typical Propagation Delays • ESD Protection: >2 kV Human Body Model • The 100 Series Contains Temperature Compensation. • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V • Internal Input 75 kW Pulldown Resistors • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity: Pb Pkg Level 1, Pb−Free Pkg Level 3 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 347 devices • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAM* A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package SO−20 WB DW SUFFIX CASE 751D 20 1 100LVEL30 AWLYYWWG |
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