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CAT24C05 Datasheet(PDF) 4 Page - Catalyst Semiconductor

Part No. CAT24C05
Description  2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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CAT24C05 Datasheet(HTML) 4 Page - Catalyst Semiconductor

 
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CAT24C03/05
4
Doc. No. 1116, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POWER-ON RESET (POR)
The CAT24C03/05 incorporates Power-On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state.
The CAT24C03/05 devicewillpowerupintoStandbymode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device ad-
dress when cascading multiple devices. When not driven,
these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits the write opera-
tions for upper half of memory, when pulled HIGH. When
not driven, this pin is pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24C03/05 supports the Inter-Integrated Circuit
(I2C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock and
all START and STOP conditions. The CAT24C03/05 acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver.
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. For normal Read/Write opera-
tions, the first 4 bits of the Slave address are fixed at
1010 (Ah). The next 3 bits are used as programmable
address bits when cascading multiple devices and/or as
internal address bits. The last bit of the slave address,
R/W, specifies whether a Read (1) or Write (0) opera-
tion is to be performed. The 3 address space extension
bits are assigned as illustrated in Figure 2. A2, A1 and
A0 must match the state of the external address pins,
and a8 (CAT24C05) is internal address bit.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9th clock cycle. As long as the Master acknowledges
the data, the Slave will continue transmitting. The Master
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.


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