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MC100EP16VC Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC100EP16VC
Description  3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC100EP16VC Datasheet(HTML) 1 Page - ON Semiconductor

 
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© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 5
1
Publication Order Number:
MC10EP16VC/D
MC100EP16VC
3.3V/5VECL Differential
Receiver/Driver with High
Gain and Enable Output
Description
The EP16VC is a differential receiver/driver. The device is
functionally equivalent to the EP16 and LVEP16 devices but with high
gain and enable output.
The EP16VC provides an EN input which is synchronized with the
data input (D) signal in a way that provides glitchless gating of the
QHG and QHG outputs.
When the EN signal is LOW, the input is passed to the outputs and
the data output equals the data input. When the data input is HIGH and
EN goes HIGH, it will force the QHG LOW and the QHG HIGH on the
next negative transition of the data input. If the data input is LOW
when the EN goes HIGH, the next data transition to a HIGH is ignored
and QHG remains LOW and QHG remains HIGH. The next positive
transition of the data input is not passed on to the data outputs under
these conditions. The QHG and QHG outputs remain in their disabled
state as long as the EN input is held HIGH. The EN input has no
influence on the Q output and the data input is passed on (inverted) to
this output whether EN is HIGH or LOW. This configuration is ideal
for crystal oscillator applications where the oscillator can be free
running and gated on and off synchronously without adding extra
counts to the output.
The VBB/D pin is internally dedicated and available for differential
interconnect. VBB/D may rebias AC coupled inputs. When used,
decouple VBB/D and VCC via a 0.01 mF capacitor and limit current
sourcing or sinking to 1.5 mA. When not used, VBB/D should be left
open.
The 100 Series contains temperature compensation.
Features
310 ps Typical Prop Delay Q,
380 ps Typical Prop Delay QHG, QHG
Gain > 200
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
Open Input Default State
QHG Output Will Default LOW with D Inputs Open or at VEE
VBB Output
Pb−Free Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
M
= Date Code
G
= Pb−Free Package
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R
ALYWG
G
KP66
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
8
KEP66
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
14
(Note: Microdot may be in either location)


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