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SN74ABT18245ADLR Datasheet(PDF) 11 Page - Texas Instruments |
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SN74ABT18245ADLR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 32 page SN54ABT18245A, SN74ABT18245A SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 instruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction. Table 3. Instruction-Register Opcodes BINARY CODE† BIT 7 → BIT 0 MSB → LSB SCOPE OPCODE DESCRIPTION SELECTED DATA REGISTER MODE 00000000 EXTEST Boundary scan Boundary scan Test 10000001 IDCODE Identification read Device identification Normal 10000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal 00000011 BYPASS‡ Bypass scan Bypass Normal 10000100 BYPASS‡ Bypass scan Bypass Normal 00000101 BYPASS‡ Bypass scan Bypass Normal 00000110 HIGHZ Control boundary to high impedance Bypass Modified test 10000111 CLAMP Control boundary to 1/0 Bypass Test 10001000 BYPASS‡ Bypass scan Bypass Normal 00001001 RUNT Boundary-run test Bypass Test 00001010 READBN Boundary read Boundary scan Normal 10001011 READBT Boundary read Boundary scan Test 00001100 CELLTST Boundary self test Boundary scan Normal 10001101 TOPHIP Boundary toggle outputs Bypass Test 10001110 SCANCN Boundary-control register scan Boundary control Normal 00001111 SCANCT Boundary-control register scan Boundary control Test All others BYPASS Bypass scan Bypass Normal † Bit 7 is used to maintain even parity in the 8-bit instruction. ‡ The BYPASS instruction is executed in lieu of a SCOPE ™ instruction that is not supported in the ’ABT18245A. boundary scan This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST instruction. The BSR is selected in the scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at the device I/O pins is passed through the I/O BSCs to the normal on-chip logic. For I/O pins, the operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 43–40 of the BSR). When a given output enable is active (logic 1), the associated I/O pins operate in the output mode. Otherwise, the I/O pins operate in the input mode. The device operates in the test mode. identification read This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the scan path. The device operates in the normal mode. sample boundary This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs associated with I/O pins in the output mode. The device operates in the normal mode. |
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