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MC74VHC1GT50 Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC74VHC1GT50
Description  Noninverting Buffer / CMOS Logic Level Shifter TTL−Compatible Inputs
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC74VHC1GT50 Datasheet(HTML) 1 Page - ON Semiconductor

   
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© Semiconductor Components Industries, LLC, 2007
February, 2007 − Rev. 13
1
Publication Order Number:
MC74VHC1GT50/D
MC74VHC1GT50
Noninverting Buffer /
CMOS Logic Level Shifter
TTL−Compatible Inputs
The MC74VHC1GT50 is a single gate noninverting buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT50 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT50 to be used to interface high voltage to
low voltage circuits. The output structures also provide protection
when VCC = 0 V. These input and output structures help prevent
device destruction caused by supply voltage − input/output voltage
mismatch, battery backup, hot insertion, etc.
Features
Designed for 1.65 V to 5.5 VCC Operation
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V, VCC = 5 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 104; Equivalent Gates = 26
Pb−Free Packages are Available
Figure 1. Pinout (Top View)
IN A
OUT Y
1
VCC
NC
IN A
OUT Y
GND
Figure 2. Logic Symbol
1
2
34
5
PIN ASSIGNMENT
1
2
3
GND
NC
IN A
4
5VCC
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
H
A Input
Y Output
L
H
SC−88A/SOT−353/SC−70
DF SUFFIX
CASE 419A
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
MARKING
DIAGRAMS
http://onsemi.com
1
5
1
5
1
5
VL M
G
G
VL
= Device Code
M
= Date Code*
G
= Pb−Free Package
1
5
VL M
G
G
*Date Code orientation and/or position may vary
depending upon manufacturing location.
(Note: Microdot may be in either location)


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