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74F109 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74F109
Description  Dual JK Positive Edge-Triggered Flip-Flop
Download  7 Pages
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74F109 Datasheet(HTML) 2 Page - Fairchild Semiconductor

   
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Truth Table
H (h)
= HIGH Voltage Level
L (l)
= LOW Voltage Level
 = LOW-to-HIGH Transition
X
= Immaterial
Q0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Unit Loading/Fan Out
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
SD
CD
CP
J
K
QQ
L
H
XXX
H
L
H
L
XXX
L
H
L
L
XXX
H
H
HH

II
L
H
HH

hI
Toggle
HH

Ih
Q
Q
HH

hh
H
L
HH
L
X
XQ
Q
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
J1, J2, K1, K2
Data Inputs
1.0/1.0
20
µA/−0.6 mA
CP1, CP2
Clock Pulse Inputs (Active Rising Edge)
1.0/1.0
20
µA/−0.6 mA
CD1, CD2
Direct Clear Inputs (Active LOW)
1.0/3.0
20
µA/−1.8 mA
SD1, SD2
Direct Set Inputs (Active LOW)
1.0/3.0
20
µA/−1.8 mA
Q1, Q2, Q1, Q2 Outputs
50/33.3
−1 mA/20 mA


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