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74F109 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. 74F109
Description  Dual JK Positive Edge-Triggered Flip-Flop
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74F109 Datasheet(HTML) 1 Page - Fairchild Semiconductor

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© 2000 Fairchild Semiconductor Corporation
April 1988
Revised September 2000
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D-type flip-flop (refer
to F74 data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes
both Q and Q HIGH
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Order Number
Package Number
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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