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A3950 Datasheet(PDF) 1 Page - Allegro MicroSystems

Part No. A3950
Description  DMOS Full-Bridge Motor Driver
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Maker  ALLEGRO [Allegro MicroSystems]
Homepage  http://www.allegromicro.com
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A3950 Datasheet(HTML) 1 Page - Allegro MicroSystems

 
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Package LP, 16 pin TSSOP
with Exposed Thermal Pad
Description
Designed for PWM (pulse width modulated) control of dc
motors, the A3950 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM control signals. Internal synchronous rectification
control circuitry is provided to lower power dissipation during
PWM operation.
Internal circuit protection includes motor lead short-to-
supply / short-to-ground, thermal shutdown with hysteresis,
undervoltage monitoring of VBB andVCP, and crossover-current
protection.
TheA3950 is supplied in a thin profile (<1.2 mm overall height)
16 pin TSSOP package (LP), and a very thin (0.75 mm nominal
height) QFN package. Both packages provide an exposed pad
for enhanced thermal dissipation, and are lead (Pb) free with
100% matte tin leadframe plating.
A3950DS, Rev. 4
Features and Benefits
▪ Low RDS(on) outputs
▪ Overcurrent protection
▪ Motor lead short-to-supply protection
▪ Short-to-ground protection
▪ Sleep function
▪ Synchronous rectification
▪ Diagnostic output
▪ Internal undervoltage lockout (UVLO)
▪ Crossover-current protection
DMOS Full-Bridge Motor Driver
Packages:
Typical Application Diagrams
A3950
Package EU, 16 pin QFN
with Exposed Thermal Pad
Package LP
Package EU
VBB
0.1 μF
50 V
0.22 μF
25 V
100 μF
50 V
0.1 μF
50 V
0.1 μF
50 V
A3950
EU Package
VDD
5 kΩ
PHASE
GND
SLEEP
ENABLE
GND
CP2
CP1
OUTB
VBB
0.1 μF
50 V
0.22 μF
25 V
0.1 μF
50 V
0.1 μF
50 V
100 μF
50 V
A3950
LP Package
VDD
5 kΩ
SLEEP
ENABLE
OUTA
SENSE
NFAULT
MODE
PHASE
GND
OUTB
VBB
VCP
GND
CP2
CP1
VREG
NC


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