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MC74HCT74A Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC74HCT74A
Description  Dual D Flip−Flop with Set and Reset with LSTTL Compatible Inputs
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC74HCT74A Datasheet(HTML) 1 Page - ON Semiconductor

   
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© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 10
1
Publication Order Number:
MC74HCT74A/D
MC74HCT74A
Dual D Flip−Flop with Set
and Reset with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 136 FETs or 34 Equivalent Gates
Pb−Free Packages are Available
LOGIC DIAGRAM
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
PIN 14 = VCC
PIN 7 = GND
Design Criteria
Value
Units
Internal Gate Count†
34
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
Speed Power Product
.0075
pJ
†Equivalent to a two−input NAND gate.
http://onsemi.com
MARKING
DIAGRAMS
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G= Pb−Free Package
SOIC−14
D SUFFIX
CASE 751A
14
1
HCT74AG
AWLYWW
1
14
14
1
PDIP−14
N SUFFIX
CASE 646
MC74HCT74AN
AWLYYWWG
1
14
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
PIN ASSIGNMENT
SET 1
CLOCK 1
DATA 1
RESET 1
11
12
13
14
8
9
10
5
4
3
2
1
7
6
SET 2
CLOCK 2
DATA 2
RESET 2
VCC
Q2
Q2
GND
Q1
Q1
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data
Q
Q
LH
X
X
HL
HL
X
X
L
H
L
L
X
X
H*
H*
HH
H
H
L
HH
L
L
H
H
H
L
X
No Change
H
H
H
X
No Change
H
H
X
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredict-
able if Set and Reset go high simultaneously.


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