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MC10EP446 Datasheet(PDF) 16 Page - ON Semiconductor

Part No. MC10EP446
Description  3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC10EP446 Datasheet(HTML) 16 Page - ON Semiconductor

 
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MC10EP446, MC100EP446
http://onsemi.com
16
The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will
suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the
falling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resume
all activities (Figure 13).
Figure 13. Timing Diagram with CKEN with CKSEL HIGH
CLK
CKEN
SOUT
CKSEL
D1−1
D0−1D2−1D3−1
PCLK
D4−1D5−1
Internal Clock
Disabled
Internal Clock
Enabled
The differential PCLK output (Pins 14 and 15) is a word
framer and can help the user synchronize the serial data
output, SOUT (Pins 11 and 12), in their applications.
Furthermore, PCLK can be used as a trigger for input
parallel data (Figure 14).
An internally generated voltage supply, the VBB pin, is
available to this device only. For single–ended input
conditions, the unused differential input is connected to VBB
as a switching reference voltage. VBB may also rebias AC
coupled inputs. When used, decouple VBB and VCC via a
0.01
mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open. Also, both
outputs of the differential pair must be terminated (50
W to
VTT) even if only one output is used.
Figure 14. PCLK as Trigger Application
TRIGGER
Pattern Generator
Data Format Logic
(FPGA, ASIC)
CLK
PCLK
EP446
SYNC
SOUT SERIAL DATA
CLK
RESET


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