MC44605 datasheet(17/20 Pages) ONSEMI

Part #	MC44605

Description	High Safety, Latched Mode, GreenLine TM PWM Controller for (Multi) Synchronized Applications

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MC44605

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17

Consequently, by replacing VOHD by 2.5 V (threshold

value) in the last equation, the value ROHD to use, can be

deducted:

R

OHD +

2.5

R

ref

R

dson

3

Γ

OHD

R 2

S

(pon)max

where: (pon)max are the maximum on time losses that are

acceptable.

Disabling Block Section

This section consists of a “definitive inhibition latch”

(directly supplied by the Vcc) that disables the output (the

output is forced to zero).

In effect, this block aims at definitively disabling the

circuit when one of the following faults is detected:

— a Winding Short Circuit

— too high synchronization pulses

— a too high input power

— a too high power switch (MOSFET) heating

The signals corresponding to these faults are high when a

fault is detected (for instance, when the input power is

detected as too high, DisMPL is high).

When one (or several) of these four faults is detected, a

current source charges Cext (with a certain duty cycle) and

when its voltage becomes higher than Vref, the definitive

inhibition latch is activated. Thus, the circuit gets

definitively disabled after a delay depending on Cext.

According to the detected fault, the current that charges

Cext is not the same:

The typical values are:

— 260

mA for EHTOVP and WSCD

— 8.5

mA for OHD and MPL

when Rref is equal to 10 kW.

Figure 15. Disabling Block

2.5 V

DisOHD

DisMPL

Vref

3.4% Iref

MC44605

Pin 12

10

Definitive

Inhibition

Latch

VCC

Output

Buffer

Vref

104% Iref

E.H.T.OVP

Q S

R

VWSCD

Delay

4

mS

10

This latch is reset when the Vcc falls down to about 3.0 V.

In this case, if a new startup is performed, the circuit will

work normally (until this fault or another one is detected).

Practically, to re−start after a fault has shutdown the

circuit, the converter must be turned off for a time long

enough to enable the Vcc capacitor discharge (repair time...).

Note: As VWSCD is generally a really narrow pulse, it is

necessary to add a latch and a delay to build a 4

ms width

pulse when VWSCD becomes high.

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