Electronic Components Datasheet Search |
|
ISL9206 Datasheet(PDF) 8 Page - Intersil Corporation |
|
ISL9206 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 17 page 8 FN9260.2 January 5, 2007 XSD Host Bus Interface Communication with the host is achieved through XSD, a light-weight subset of Intersil’s ISD single-wire bus interface. XSD is a programmable-rate pseudo-synchronous bidirectional host-initiated instruction-based serial communication interface that allows up to two slave devices to be attached and addressed separately. It includes features to enable quick and reliable communication. The communication protocol is optimized for efficient transfer of data between the device and the host. The list below outlines the features supported by the XSD bus interface: • Programmable bit rate up to 23kbps • Up to 2 devices can be connected to the host and addressed separately • 16-Bit host instruction frame supports multi-byte register read and write • Built-in communication error detection • CRC generation capability • Supports interrupt signaling • Integrated bus inactivity detector for automatic activation of sleep mode XSD BUS PHYSICAL MODEL The physical model of the XSD bus is shown in Figure 7. The model shows a single-wire connection between the host and the device, not including the ground signal. The input logic on the device side is designed to be compatible with any voltage between 1.8V to 5.0V. The host interface should contain an open-drain or open-collector output. The pull-up resister RPU can be connected either to the host supply voltage VDDH or the device supply voltage VDDD. Typically the host supply voltage should be used for pull-up. DATA TRANSFER PROTOCOL To initiate a transaction, the host first sends a 16-Bit instruction frame to the device, followed by data byte frame(s) if the instruction is a write operation. The instruction frame consists of a chip-select code, operation code, register bank and address pointer, and number of data bytes information, as shown in Figure 9. If the instruction is a read operation, the device will return 1 to 17 byte frames of data back to the host. The serial data transfer always takes place with the LSB first. The following explains the bus symbols and the transaction frames are introduced in later sections. BUS SIGNALING SYMBOLS The XSD bus is nominally held high. Various bus symbols and commands are generated by active-low pulse width modulation. Following are the set of valid bus signaling symbols supported by the XSD interface: 1) break (issued by host): • used to wake the device up from Sleep mode (Note: a narrow ‘break’ can also be used to wake up the device from the Sleep mode, as described in the Power-on Reset section) • used to reset the device’s XSD bit counters and time qualifiers • used to signal a change in communication channel (from one slave device to another) 2) break (issued by device): • used as ‘device-ready’ indication to the host (after a Soft-reset or wake up from Sleep mode) • used as an interrupt indicator 3) ‘1’ symbol: • used for instruction and data coding 4) ‘0’ symbol: • used for instruction and data coding SYMBOL TIMING DEFINITIONS Symbol timings are defined in terms of bit-time (BT), determined by the selected bus transfer bit-rate pre-programmed into the device’s OTP ROM location 0-00[5:4]. Selectable bus speeds are: 2.89kHz (x = 0.5), 5.78kHz (x = 1), 11.56kHz (x = 2) and 23.12kHz (x = 4). An instruction or data frame consists of a sequence of ‘1’ and/or ‘0’ symbols. Figure 8 illustrates the timing definitions. A ‘1’ symbol is nominally 0.3 BT wide while a ‘0’ symbol is nominally 0.7 BT wide. One ‘1’ or ‘0’ symbol is represented in each BT period. Any detected pulse width less than 0.124 BT wide will be interpreted as a glitch and will result in a bus error. Table 2 and 3 summarize the timing definitions of all TABLE 1. INTERRUPT EVENT SUMMARY CONDITION INTERRUPT ENABLE BIT INTERRUPT STATUS FLAG INTERRUPT EVENT OTP ROM Write-in- Progress eEEW (fixed) sEEW Accessing the ISL9206 during an on-going ROM write process (used only during initial OTP ROM programming). XSD Bus Error eINT sBER XSD bus error or invalid instruction frame detected. Improper authentication sequence detected. Register Access Error eINT sACC Accessing protected registers. ISL9206 |
Similar Part No. - ISL9206_07 |
|
Similar Description - ISL9206_07 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |