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IRS2168DPBF Datasheet(PDF) 15 Page - International Rectifier

Part No. IRS2168DPBF
Description  ADVANCED PFC BALLAST CONTROL IC
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Maker  IRF [International Rectifier]
Homepage  http://www.irf.com
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IRS2168DPBF Datasheet(HTML) 15 Page - International Rectifier

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IRS2168D(S)PbF
www.irf.com
Page 15
II. PFC Section
Functional Description
In most electronic ballasts it is necessary to have the
circuit act as a pure resistive load to the AC input line
voltage. The degree to which the circuit matches a pure
resistor is measured by the phase shift between the input
voltage and input current and how well the shape of the
input current waveform matches the shape of the
sinusoidal input voltage. The cosine of the phase angle
between the input voltage and input current is defined as
the power factor (PF), and how well the shape of the input
current waveform matches the shape of the input voltage
is determined by the total harmonic distortion (THD). A
power factor of 1.0 (maximum) corresponds to zero
phase shift and a THD of 0% and represents a pure
sinusoidal waveform (no distortion). For this reason it is
desirable to have a high PF and a low THD. To achieve
this, the IRS2168D includes an active power factor
correction (PFC) circuit.
The control method implemented in the IRS2168D is for a
boost-type
converter
(Fig.
10)
running
in
critical-
conduction mode (CCM). This means that during each
switching cycle of the PFC MOSFET, the circuit waits
until the inductor current discharges to zero before turning
the PFC MOSFET on again. The PFC MOSFET is turned
on and off at a much higher frequency (>10 kHz) than the
line input frequency (50 to 60 Hz).
CBUS
+
(+)
(-)
MPFC
LPFC
DPFC
DC Bus
Figure 10:
Boost converter circuit
When the switch MPFC is turned on, the inductor LPFC is
connected between the rectified line input (+) and (-)
causing the current in LPFC to charge up linearly. When
MPFC is turned off, LPFC is connected between the rectified
line input (+) and the DC bus capacitor CBUS (through
diode DPFC) and the stored current in LPFC flows into CBUS.
MPFC is turned on and off at a high frequency and the
voltage on CBUS charges up to a specified voltage. The
feedback loop of the IRS2168D regulates this voltage to a
fixed value by continuously monitoring the DC bus
voltage and adjusting the on-time of MPFC accordingly.
For an increasing DC bus the on-time is decreased, and
for a decreasing DC bus the on-time is increased. This
negative feedback control is performed with a slow loop
speed and a low loop gain such that the average inductor
current smoothly follows the low-frequency line input
voltage for high power factor and low THD. The on-time
of MPFC therefore appears to be fixed (with an additional
modulation to be discussed later) over several cycles of
the line voltage.
With a fixed on-time, and an off-time
determined by the inductor current discharging to zero,
the result is a system where the switching frequency is
free-running
and
constantly changing
from
a
high
frequency near the zero crossing of the AC input line
voltage, to a lower frequency at the peaks (Fig. 11).
V, I
t
Figure 11:
Sinusoidal line input voltage (solid line),
triangular PFC Inductor current and smoothed sinusoidal
line input current (dashed line) over one half-cycle of the
AC line input voltage
When the line input voltage is low (near the zero
crossing), the inductor current will charge up to a small
amount and the discharge time will be fast resulting in a
high switching frequency. When the input line voltage is
high (near the peak), the inductor current will charge up to
a higher amount and the discharge time will be longer
giving a lower switching frequency.
The PFC control circuit of the IRS2168D (Fig. 12)
includes five control pins: VBUS, COMP, ZX, PFC and OC.
The VBUS pin measures the DC bus voltage via an
external resistor voltage divider. The COMP pin programs
the on-time of MPFC and the speed of the feedback loop
with an external capacitor. The ZX pin detects when the
inductor current discharges to zero each switching cycle
using a secondary winding from the PFC inductor. The PFC
pin is the low-side gate driver output for the external
MOSFET, MPFC. The OC pin senses the current flowing
through MPFC and performs cycle-by-cycle over-current
protection.
RVBUS1
RVBUS2
RVBUS
CCOMP
LPFC
MPFC
RPFC
DFPC
CBUS
(+)
(-)
RZX
PFC
Control
VBUS
COMP
PFC
ZX
COM
OC
ROC
Figure 12:
IRS2168D simplified PFC control circuit
The VBUS pin is regulated against a fixed internal 4.0 V
reference voltage for regulating the DC bus voltage (Fig.
13). The feedback loop is performed by an operational
transconductance amplifier (OTA) that sinks or sources a
current to the external capacitor at the COMP pin. The
resulting voltage on the COMP pin sets the threshold for
the charging of the internal timing capacitor (C1, Figure
13) and therefore programs the on-time of MPFC. During
preheat and ignition modes of the ballast section, the gain
of the OTA is set to a high level to raise the DC bus level
quickly and to minimize the transient on the DC bus that
can occur during ignition. During run mode, the gain is
then decreased to a lower level necessary for a slower


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