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CS51313 Datasheet(PDF) 1 Page - ON Semiconductor |
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CS51313 Datasheet(HTML) 1 Page - ON Semiconductor |
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© Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 8 1 Publication Order Number: CS51313/D CS51313 Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators The CS51313 is a synchronous dual NFET Buck Regulator Controller. It is designed to power the core logic of the latest high performance CPUs. It uses the V2™ control method to achieve the fastest possible transient response and best overall regulation. It incorporates many additional features required to ensure the proper operation and protection of the CPU and Power system. The CS51313 provides the industry’s most highly integrated solution, minimizing external component count, total solution size, and cost. The CS51313 is specifically designed to power Intel’s Pentium® II processor and includes the following features: 5−bit DAC with 1.2% tolerance, Power Good output, overcurrent hiccup mode protection, overvoltage protection, VCC monitor, Soft Start, adaptive voltage positioning and adaptive FET non−overlap time. A precision reference trimmed to 1.0% is also externally available for use by other regulators. The CS51313 will operate over an 8.4 V to 14 V range and is available in 16 lead narrow body surface mount package. Features • Synchronous Switching Regulator Controller for CPU VCORE • Dual N−Channel MOSFET Synchronous Buck Design • V2 Control Topology • 200 ns Transient Loop Response • 5−Bit DAC with 1.2% Tolerance • Hiccup Mode Overcurrent Protection • 40 ns Gate Rise and Fall Times (3.3 nF Load) • 65 ns Adaptive FET Non−Overlap Time • Adaptive Voltage Positioning • Power Good Output Monitors Regulator Output • VCC Monitor Provides Undervoltage Lockout • OVP Output Monitors Regulator Output • Enable Through Use of the COMP Pin • +1.23 V Reference Voltage Available Externally http://onsemi.com Device Package Shipping ORDERING INFORMATION CS51313GD16 SO−16 48 Units/Rail CS51313GDR16 SO−16 2500 Tape & Reel PIN CONNECTIONS MARKING DIAGRAM SO−16 D SUFFIX CASE 751B A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week 1 CS51313 AWLYWW 16 1 16 VCC VOUT 1 16 GATE(H) VFB GND VID4 GATE(L) VREF OVP VID3 PWRGD VID2 COFF VID1 COMP VID0 |
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