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CS8129 Datasheet(PDF) 6 Page - ON Semiconductor

Part No. CS8129
Description  5.0 V, 750 mA Low Dropout Linear Regulator with Lower RESET Threshold
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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CS8129 Datasheet(HTML) 6 Page - ON Semiconductor

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CS8129
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6
CIRCUIT DESCRIPTION
The CS8129 RESET function has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1.0 V.
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram on page 2).
Low Voltage Inhibit Circuit
This circuit monitors output voltage, and when output
voltage is below the specified minimum causes the RESET
output transistor to be in the ON (saturation) state. When the
output voltage is above the specified level, this circuit permits
the RESET output transistor to go into the OFF state if
allowed by the RESET Delay circuit.
Reset Delay Circuit
This circuit provides a programmable (by external
capacitor) delay on the RESET output lead. The Delay lead
provides source current to the external delay capacitor only
when the “Low Voltage Inhibit” circuit indicates that output
voltage is above VRT(ON). Otherwise, the Delay lead sinks
current to ground (used to discharge the delay capacitor).
The discharge current is latched ON when the output voltage
is below VRT(OFF). The Delay capacitor is fully discharged
anytime the output voltage falls out of regulation, even for
a short period of time. This feature ensures that a controlled
RESET pulse is generated following detection of an error
condition. The circuit allows the RESET output transistor to
go to the OFF (open) state only when the voltage on the
Delay lead is higher than VDC(HI).
Figure 13. Test & Application Circuit
CIN*
100 nF
Delay
VOUT
RRST
COUT**
10
mF to
100
mF
RESET
CS8129
*CIN is required if regulator is far from the power source filter.
**COUT is required for stability.
VIN
GND
4.7 k
W
Delay
0.1
mF
The Delay time for the RESET function is calculated from
the formula:
Delay time
+
CDelay
VDelay Threshold
ICharge
Delay time
+ CDelay(mF) 3.2 105
If CDelay = 0.1 mF, Delay time (ms) = 32 ms ±50%: i.e.
16 ms to 48 ms. The tolerance of the capacitor must be taken
into account to calculate the total variation in the delay time.
APPLICATION NOTES
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25
°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor COUT shown in Figure
13 should work for most applications, however it is not
necessarily the optimized solution.
To determine an acceptable value for COUT for a particular
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in
step 3 and vary the input voltage until the oscillations
increase. This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.


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