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CS5155H Datasheet(PDF) 6 Page - ON Semiconductor

Part No. CS5155H
Description  CPU 5−Bit Synchronous Buck Controller
Download  17 Pages
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS5155H Datasheet(HTML) 6 Page - ON Semiconductor

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CS5155H
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6
Figure 2. Block Diagram
+
+
+
VCC1
SS
VID0
VID1
VID2
VID3
VID4
VFFB Low
Comparator
VFFB
Fast Feedback
LGnd
Slow Feedback
PWM
Comparator
SS Low
Comparator
SS High
Comparator
5 BIT
DAC
VCC1 Monitor
Comparator
Error
Amplifier
VCC1
VCC2
COFF
VGATE(H)
VGATE(L)
PGnd
FAULT
FAULT
FAULT
Latch
PGnd
R
S
Q
Q
R
S
Q
Q
R
S
Q
Latch
PMW
COFF
One Shot
Off−Time
Timeout
Time−Out
Timer
Edge Triggered
Extended
Off−Time
Timeout
Normal
Off−Time
Timeout
Maximum
On−Time
Timeout
(30 μs)
GATE(H) = ON
GATE(H) = OFF
2.0 μA
60 μA
5.0 V
0.7 V
2.5 V
1.0 V
+
+
+
3.90 V
3.85V
VFB
COMP
PWM COMP
APPLICATIONS INFORMATION
THEORY OF OPERATION
V2 Control Method
The V2 method of control uses a ramp signal that is
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is
generated from the output voltage itself. This control
scheme inherently compensates for variation in either line or
load conditions, since the ramp signal is generated from the
output voltage itself. This control scheme differs from
traditional techniques such as voltage mode, which
generates an artificial ramp, and current mode, which
generates a ramp from inductor current.
Figure 3. V2 Control Diagram
COMP
VFFB
Reference
Voltage
+
+
PWM
Comparator
Ramp
Signal
Error
Amplifier
Error
Signal
Output
Voltage
Feedback
VFB
VGATE(L)
E
C
VGATE(H)


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