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CS5112 Datasheet(PDF) 6 Page - ON Semiconductor

Part No. CS5112
Description  1.4 A Switching Regulator with 5.0 V, 100 mA Linear Regulator with Watchdog, RESET and ENABLE
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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CS5112 Datasheet(HTML) 6 Page - ON Semiconductor

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CS5112
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6
CIRCUIT DESCRIPTION
VREG
+
Bandgap
Reference
1.25 V
IBIAS
RBIAS
64.9 k
W
CDelay
WDI
RESET &
Watchdog Timer
Over
Temperature
Current
Limit
Linear
Error
Amplifier
R1
Q2
Q1
Q3
R2
R3
R4
R5
VLIN
COUT = 100 mF
ESR < 8.0
W
RESET
Figure 6. Block Diagram of 5.0 V Linear Regulator Portion of the CS5112
5.0 V LINEAR REGULATOR
The 5.0 V linear regulator consists of an error amplifier,
bandgap voltage reference, and a composite pass transistor.
The 5.0 V linear regulator circuitry is shown in Figure 6.
When an unregulated voltage greater than 6.6 V is applied
to the VREG input, a 5.0 V regulated DC voltage will be
present at VLIN. For proper operation of the 5.0 V linear
regulator, the IBIAS lead must have a 64.9 kW pull down
resistor to ground. A 100
mF or larger capacitor with an ESR
< 8.0
W must be connected between VLIN and ground. To
operate the 5.0 V linear regulator as an independent
regulator (i.e. separate from the switching supply), the input
voltage must be tied to the VREG lead.
As the voltage at the VREG input is increased, Q1 is turned
on. Q1 provides base drive for Q2 which in turn provides
base current for Q3. As Q3 is turned on, the output voltage,
VLIN, begins to rise as Q3’s output current charges the output
capacitor, COUT. Once VLIN rises to a certain level, the error
amplifier becomes biased and provides the appropriate
amount of base current to Q1. The error amplifier monitors
the scaled output voltage via an internal voltage divider, R2
through R5, and compares it to the bandgap voltage
reference. The error amplifier output or error signal is an
output current equal to the error amplifier’s input
differential voltage times the transconductance of the
amplifier. Therefore, the error amplifier varies the base
current to Q1, which provides bias to Q2 and Q3, based on the
difference between the reference voltage and the scaled
VLIN output voltage.
CONTROL FUNCTIONS
The watchdog timer circuitry monitors an input signal
(WDI) from the microprocessor. It responds to the falling
edge of this watchdog signal which it expects to see within
an externally programmable time (see Figure 7).
The watchdog time is given by:
tWDI + 1.353
CDelayRBIAS
Using CDelay = 0.1 mF and RBIAS = 64.9 kW gives a time
ranging from 6.25 ms to 11 ms assuming ideal components.
Based on this, the software must be written so that the
watchdog arrives at least every 6.25 ms. In practice, the
tolerance of CDelay and RBIAS must be taken into account
when calculating the minimum watchdog time (tWDI).
RESET
VREG
WDI
VLIN
Normal Operation
tPOR
Figure 7. Timing Diagram for Normal
Regulator Operation
If a correct watchdog signal is not received within the
specified time a reset pulse train is issued until the correct
watchdog signal is received. The nominal reset signal in this
case is a 5 volt square wave with a 50% duty cycle as shown
in Figure 8.


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