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IS61LV2568 Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS61LV2568 Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 9 page Integrated Silicon Solution, Inc. — 1-800-379-4774 1 Rev. B 02/07/03 IS61LV2568 ISSI® Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. FEBRUARY 2003 FEATURES • High-speed access times: 10 and 12 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Low power: 540 mW @ 10 ns 36 mW standby mode • TTL compatible inputs and outputs • Single 3.3V ±10% power supply • Packages available: – 36-pin 400-mil SOJ – 44-pin TSOP (Type II) DESCRIPTION The ISSI IS61LV2568 is a very high-speed, low power, 262,144-word by 8-bit CMOS static RAM. The IS61LV2568 is fabricated using ISSI's high-performance CMOS tech- nology. This highly reliable process coupled with innova- tive circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 36mW (max.) with CMOS input levels. The IS61LV2568 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV2568 is available in 36-pin 400-mil SOJ, and 44-pin TSOP (Type II) packages. FUNCTIONAL BLOCK DIAGRAM A0-A17 CE OE WE 256K X 8 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VDD I/O DATA CIRCUIT I/O0-I/O7 256K x 8 HIGH-SPEED CMOS STATIC RAM |
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