M58LR128HT datasheet(40/112 Pages) STMICROELECTRONICS

Part #	M58LR128HT

Description	128 Mbit (8 Mb 횞16, Multiple Bank, Multilevel interface, Burst) 1.8 V supply Flash memories

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Configuration Register

M58LR128HT, M58LR128HB

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6.7

Valid Clock Edge bit (CR6)

The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during

synchronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling

edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the

rising edge of the Clock is the active edge.

6.8

Wrap Burst bit (CR3)

The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst

reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the

boundary (no wrap).

When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’)

the burst read does not wrap.

6.9

Burst length bits (CR2-CR0)

The Burst Length bits are used to set the number of Words to be output during a

Synchronous Burst Read operation as result of a single address latch cycle.

They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words

are read sequentially. In continuous burst mode the burst sequence can cross bank

boundaries.

In continuous burst mode, in 4, 8 or 16 Words no-wrap, depending on the starting address,

the device asserts the WAIT signal to indicate that a delay is necessary before the data is

output.

If the starting address is shifted by 1, 2 or 3 positions from the four-Word boundary, WAIT is

asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first

16-Word boundary, to indicate that the device needs an internal delay to read the

successive Words in the array. WAIT will be asserted only once during a continuous burst

access. See also Table 12: Burst type definition.

CR14, CR5 and CR4 are reserved for future use.

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