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SY89221UHYTR Datasheet(PDF) 8 Page - Micrel Semiconductor

Part # SY89221UHYTR
Description  Precision 1:15 LVPECL Fanout Buffer with 2:1 MUX and Four 첨1/첨2/첨4 Clock Divider Output Banks
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY89221UHYTR Datasheet(HTML) 8 Page - Micrel Semiconductor

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Micrel, Inc.
SY89221U
January 2007
8
M9999-012407-B
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
(8)
VCC = +2.5V ±5% or 3.3V ±10%, TA = –40°C to +85°C, RL = 50Ω to VCC–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
VOUT ≥ 400mV
1.5
2.0
GHz
IN-to-Q
800
1250
1600
ps
CLK_SEL-to-Q
700
1000
1400
ps
tPD
Differential Propagation Delay
/MR(H-L)-to-Q
700
1000
1400
ps
tRR
Reset Recovery Time
/MR (L-H)-to-IN
300
ps
tPD
Tempco
Differential Propagation Delay
Temperature Coefficient
225
fs/°C
Within-Bank Skew
Within same fanout bank
(9, 10)
10
35
ps
Bank-to-Bank Skew
Same divide setting
(11)
15
40
ps
Bank-to-Bank Skew
Different divide setting
(11)
25
60
ps
tSKEW
Part-to-Part Skew
Note 12
400
ps
Random Jitter (RJ)
Note 13
1
psRMS
Total Jitter (TJ)
Note 14
10
psPP
tJITTER
Cycle-to-Cycle Jitter
Note 15
1
psRMS
tr, tf
Output Rise/Fall Time
(20% to 80%)
At full output swing
120
180
270
ps
Divide-by-2 or Divide-by-4
47
53
Divide-by-1, input > 1GHz
45
55
%
Duty Cycle
Divide-by-1, input < 1GHz
47
53
Notes:
8.
Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC-parameters are guaranteed
by design and characterization.
9.
Within-bank skew is the difference in propagation delays among the outputs within the same bank.
10. Skews within banks depend on the number of outputs. Within-bank skew decreases if the bank has lesser outputs.
11. Bank-to-bank skew is the difference in propagation delays between outputs from different banks. Bank-to-bank skew is also the phase offset
between each bank, after MR is applied.
12. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
13. Random jitter is measured with a K28.7 comma detect character pattern.
14. Total jitter definition: with an ideal clock input frequency
≤ f
MAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output
signal.


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