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SN74LV595APWT Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LV595APWT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 22 page SN54LV595A, SN74LV595A 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS414N − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH′ are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS FUNCTION SER SRCLK SRCLR RCLK OE FUNCTION X X X X H Outputs QA−QH are disabled. X X X X L Outputs QA−QH are enabled. X X L X X Shift register is cleared. L ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored in the storage register. |
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