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MC9S08QD4VPC Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc |
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MC9S08QD4VPC Datasheet(HTML) 67 Page - Freescale Semiconductor, Inc |
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67 / 196 page  Chapter 5 Resets, Interrupts, and General System Control MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 67 5.8.9 System Power Management Status and Control 2 Register (SPMSC2) This high-page register contains status and control bits to configure the stop mode behavior of the MCU. See Section 3.6, “Stop Modes,” for more information on stop modes. Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2) 5 LVDIE Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF. 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVDF = 1. 4 LVDRE Low-Voltage Detect Reset Enable — This write-once bit enables LVDF events to generate a hardware reset (provided LVDE = 1). 0 LVDF does not generate hardware resets. 1 Force an MCU reset when LVDF = 1. 3 LVDSE Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. 2 LVDE Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. 0 BGBE Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. 76 54 321 0 RLVWF 0 LVDV LVWV PPDF 0 PPDC1 1 This bit can be written only one time after reset. Additional writes are ignored. W LVWACK PPDACK POR: 02 2 LVWF will be set in the case when V supply transitions below the trip point or after reset and Vsupply is already below VLVW. 00 00 000 LVDR: 02 0 U U 0 000 Other Reset 02 0 U U 0 000 = Unimplemented or Reserved U = Unaffected by reset Table 5-12. SPMSC1 Register Field Descriptions (continued) Field Description |
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