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ST72104G Datasheet(PDF) 60 Page - STMicroelectronics |
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ST72104G Datasheet(HTML) 60 Page - STMicroelectronics |
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60 / 140 page  ST72104G, ST72215G, ST72216G, ST72254G 60/140 12.3 SERIAL PERIPHERAL INTERFACE (SPI) 12.3.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. Refer to the Pin Description chapter for the device- specific pin-out. 12.3.2 Main Features s Full duplex, three-wire synchronous transfers s Master or slave operation s Four master mode frequencies s Maximum slave mode frequency = fCPU/2. s Four programmable master bit rates s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision flag protection s Master mode fault protection capability. 12.3.3 General description The SPI is connected to external devices through 4 alternate pins: – MISO: Master In Slave Out pin – MOSI: Master Out Slave In pin – SCK: Serial Clock pin –SS: Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 37. The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the SCK pin). Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is com- plete. Four possible data/clock timing relationships may be chosen (see Figure 40) but master and slave must be programmed with the same timing mode. Figure 37. Serial Peripheral Interface Master/Slave 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI MOSI MISO SCK SCK SLAVE MASTER SS SS +5V MSBit LSBit MSBit LSBit |
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