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DAC8560IDDGKT Datasheet(PDF) 5 Page - Burr-Brown (TI) |
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DAC8560IDDGKT Datasheet(HTML) 5 Page - Burr-Brown (TI) |
5 / 29 page www.ti.com PIN CONFIGURATION V DD V REF V FB V OUT GND D IN SCLK SYNC 1 2 3 4 8 7 6 5 DAC8560 DAC8560 SLAS464 – DECEMBER 2006 MSOP-8 (Top View) PIN DESCRIPTIONS PIN NAME DESCRIPTION 1 VDD Power supply input, 2.7V to 5.5V. 2 VREF Reference voltage input/output. 3 VFB Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally. 4 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register, and data is sampled on subsequent falling clock edges. The DAC output updates 5 SYNC following the 24th clock. If SYNC is taken HIGH before the 24th clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC8560. Schmitt-Trigger logic Input. 6 SCLK Serial clock input. Schmitt-Trigger logic input. Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. 7 DIN Schmitt-Trigger logic Input. 8 GND Ground reference point for all circuitry on the part. 5 Submit Documentation Feedback |
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