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LAN9218-MT-E2 Datasheet(PDF) 72 Page - SMSC Corporation |
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LAN9218-MT-E2 Datasheet(HTML) 72 Page - SMSC Corporation |
72 / 130 page High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Datasheet Revision 1.5 (07-18-06) 72 SMSC LAN9218 DATASHEET 5.3.4 INT_EN—Interrupt Enable Register This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register. Offset: 5Ch Size: 32 bits BITS DESCRIPTION TYPE DEFAULT 31 Software Interrupt (SW_INT_EN) R/W 0 30:26 Reserved RO - 25 TX Stopped Interrupt Enable (TXSTOP_INT_EN) R/W 0 24 RX Stopped Interrupt Enable (RXSTOP_INT_EN) R/W 0 23 RX Dropped Frame Counter Halfway Interrupt Enable (RXDFH_INT_EN). R/W 0 22 Reserved RO 0 21 TX IOC Interrupt Enable (TIOC_INT_EN) R/W 0 20 RX DMA Interrupt (RXD_INT). R/W 0 19 GP Timer (GPT_INT_EN) R/W 0 18 PHY (PHY_INT_EN) R/W 0 17 Power Management Event Interrupt Enable (PME_INT_EN) R/W 0 16 TX Status FIFO Overflow (TXSO_EN) R/W 0 15 Receive Watchdog Time-out Interrupt (RWT_INT_EN) R/W 0 14 Receiver Error Interrupt (RXE_INT_EN) R/W 0 13 Transmitter Error Interrupt (TXE_INT_EN) R/W 0 12 Reserved RO - 11 TX Data FIFO Underrun Interrupt (TDFU_INT_EN) R/W 0 10 TX Data FIFO Overrun Interrupt (TDFO_INT_EN) R/W 0 9 TX Data FIFO Available Interrupt (TDFA_INT_EN) R/W 0 8 TX Status FIFO Full Interrupt (TSFF_INT_EN) R/W 0 7 TX Status FIFO Level Interrupt (TSFL_INT_EN) R/W 0 6 RX Dropped Frame Interrupt Enable (RXDF_INT_EN) R/W 0 5 RX Data FIFO Level Interrupt (RDFL_INT_EN) R/W 0 4 RX Status FIFO Full Interrupt (RSFF_INT_EN) R/W 0 3 RX Status FIFO Level Interrupt (RSFL_INT_EN) R/W 0 2-0 GPIO [2:0] (GPIOx_INT_EN). R/W 000 |
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Similar Description - LAN9218-MT-E2 |
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