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CD54HC194 Datasheet(PDF) 6 Page - Texas Instruments

Part No. CD54HC194
Description  High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD54HC194 Datasheet(HTML) 6 Page - Texas Instruments

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6
Set-up Time
S1, S0 to Clock (Figure 4)
tSU
-
4.5
20
-
25
-
30
-
ns
Set-up Time
DSL, DSR to Clock (Figure 4)
tSU
-
4.5
14
-
18
-
21
-
ns
Hold Time
S1, S0 to Clock (Figure 4)
tH
-
4.5
0-0-0-
ns
Hold Time
Data to Clock (Figure 3)
tH
-
4.5
0-0-0-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
TYP
MAX
MAX
MAX
HC TYPES
Propagation Delay,
Clock to Output (Figure 1)
tPLH, tPHL
CL = 50pF
2
-
175
220
265
ns
4.5
-
35
44
53
ns
6
-
30
37
45
ns
Propagation Delay,
Clock to Q
tPLH, tPHL
-
5
14
-
-
-
ns
Output Transition Time
(Figure 1)
tTLH, tTHL
CL = 50pF
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
Propagation Delay,
MR to Output (Figure 2)
tPHL
CL = 50pF
2
-
140
175
210
ns
4.5
-
28
35
42
ns
6
-
24
30
36
ns
Input Capacitance
CIN
--
-
10
10
10
pF
Maximum Clock Frequency
fMAX
-
5
60
-
-
-
MHz
Power Dissipation
Capacitance (Notes 4, 5)
CPD
-
5
55
-
-
-
pF
HCT TYPES
Propagation Delay,
Clock to Output (Figure 1)
tPLH, tPHL
CL = 50pF
4.5
-
37
46
56
ns
Propagation Delay,
Clock to Q
tPLH, tPHL
-
5
15
-
-
-
ns
Output Transition Times
(Figure 1)
tTLH, tTHL
CL = 50pF
4.5
-
15
19
22
ns
Propagation Delay,
MR to Output (Figure 2)
tPHL
CL = 50pF
4.5
-
40
50
60
ns
Input Capacitance
CIN
--
-
10
10
10
pF
Maximum Clock Frequency
fMAX
-
5
50
-
-
-
MHz
Power Dissipation
Capacitance (Notes 4, 5)
CPD
-
5
60
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC
2 f
i + ∑ (CL VCC
2) where f
i = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Prerequisite For Switching Function
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS VCC (V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
MAX
MIN
MAX
MIN
MAX


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