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EP1C12F100I8ES Datasheet(PDF) 32 Page - Altera Corporation

Part # EP1C12F100I8ES
Description  Cyclone FPGA Family Data Sheet
Download  104 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I8ES Datasheet(HTML) 32 Page - Altera Corporation

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2–26
Altera Corporation
Preliminary
January 2007
Cyclone Device Handbook, Volume 1
Figure 2–18. Input/Output Clock Mode in True Dual-Port Mode
Note (1), (2)
Notes to Figure 2–18:
(1)
All registers shown have asynchronous clear ports.
(2)
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
6
D
ENA
Q
D
ENA
Q
D
ENA
Q
data
A[ ]
address
A[ ]
Memory Block
256
× 16 (2)
512
× 8
1,024
× 4
2,048
× 2
4,096
× 1
Data In
Address A
Write/Read
Enable
Data Out
Data In
Address B
Write/Read
Enable
Data Out
clken
A
clock
A
D
ENA
Q
wren
A
6 LAB Row Clocks
q
A[ ]
6
data
B[ ]
address
B[ ]
clken
B
clock
B
wren
B
q
B[ ]
ENA
AB
ENA
D
Q
ENA
D
Q
ENA
D
Q
D
Q
D
ENA
Q
byteena
A[ ]
Byte Enable A
Byte Enable B
byteena
B[ ]
ENA
D
Q
Write
Pulse
Generator
Write
Pulse
Generator


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