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EP1C12F100I8ES Datasheet(PDF) 77 Page - Altera Corporation

Part # EP1C12F100I8ES
Description  Cyclone FPGA Family Data Sheet
Download  104 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I8ES Datasheet(HTML) 77 Page - Altera Corporation

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Altera Corporation
4–7
January 2007
Preliminary
Operating Conditions
Table 4–16. Cyclone Device Capacitance
Note (14)
Symbol
Parameter
Typical
Unit
CIO
Input capacitance for user I/O pin
4.0
pF
CLVDS
Input capacitance for dual-purpose LVDS/user I/O pin
4.7
pF
CVREF
Input capacitance for dual-purpose VREF/user I/O pin.
12.0
pF
CDPCLK
Input capacitance for dual-purpose
DPCLK/user I/O pin.
4.4
pF
CCLK
Input capacitance for CLK pin.
4.7
pF
Notes to Tables 4–1 through 4–16:
(1)
Refer to the Operating Requirements for Altera Devices Data Sheet.
(2)
Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(4)
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6)
Typical values are for TA = 25° C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(7)
VI = ground, no load, no toggling inputs.
(8)
This value is specified for normal device operation. The value may vary during power-up. This applies for all
VCCIO settings (3.3, 2.5, 1.8, and 1.5 V).
(9)
RCONF is the measured value of internal pull-up resistance when the I/O pin is tied directly to GND. RCONF value
will be lower if an external source drives the pin higher than VCCIO.
(10) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
(11) Drive strength is programmable according to values in Chapter 2, Cyclone Architecture, Table 2–11.
(12) Overdrive is possible when a 1.5 V or 1.8 V and a 2.5 V or 3.3 V input signal feeds an input pin. Turn on “Allow
voltage overdrive” for LVTTL/LVCMOS input pins in the Assignments > Device > Device and Pin Options > Pin
Placement tab when a device has this I/O combination. However, higher leakage current is expected.
(13) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels.
(14) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within
±0.5 pF.


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