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EP1C12F100I8ES Datasheet(PDF) 50 Page - Altera Corporation

Part # EP1C12F100I8ES
Description  Cyclone FPGA Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I8ES Datasheet(HTML) 50 Page - Altera Corporation

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Altera Corporation
Preliminary
January 2007
Cyclone Device Handbook, Volume 1
Figure 2–31. Control Signal Selection per IOE
In normal bidirectional operation, you can use the input register for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register is available for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, or the column and row interconnects.
Figure 2–32 shows the IOE in bidirectional configuration.
clk_out
ce_in
clk_in
ce_out
aclr/preset
sclr/preset
Dedicated I/O
Clock [5..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
oe
io_coe
io_caclr
Local
Interconnect
io_csclr
io_cce_out
io_cce_in
io_cclk


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