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ADSP-BF533SBBZ500 Datasheet(PDF) 13 Page - Analog Devices |
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ADSP-BF533SBBZ500 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 60 page  ADSP-BF533 Rev. D | Page 13 of 60 | September 2006 where the variables in the equations are: fCCLKNOM is the nominal core clock frequency fCCLKRED is the reduced core clock frequency VDDINTNOM is the nominal internal supply voltage VDDINTRED is the reduced internal supply voltage tNOM is the duration running at fCCLKNOM tRED is the duration running at fCCLKRED The percent power savings is calculated as: VOLTAGE REGULATION The Blackfin processors provide an on-chip voltage regulator that can generate processor core voltage levels 0.85 V to 1.2 V from an external 2.25 V to 3.6 V supply. Figure 5 shows the typ- ical external components required to complete the power management system.† The regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power (VDDEXT) supplied. While in hibernation, VDDEXT can still be applied, eliminating the need for external buffers. The voltage regulator can be activated from this power- down state either through an RTC wakeup or by asserting RESET, which will then initiate a boot sequence. The regulator can also be disabled and bypassed at the user’s discretion. CLOCK SIGNALS The ADSP-BF533 processor can be clocked by an external crys- tal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it must not be halted, changed, or operated below the specified frequency during normal opera- tion. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF533 processor includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 6. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental fre- quency, microprocessor-grade crystal should be used. As shown in Figure 7, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 0.5 × to 64× multiplication factor (bounded by specified minimum and max- imum VCO frequencies). The default multiplier is 10 ×, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register. All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 6 illustrates typical system clock ratios. † See EE-228: Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors. Figure 5. Voltage Regulator Circuit % power savings 1 power savings factor – () 100% × = VDDEXT VDDINT VROUT1–0 EXTERNAL COMPONENTS 2.25V TO 3.6V INPUT VOLTAGE RANGE FDS9431A ZHCS1000 100µF 1µF 10µH 0.1µF NOTE: VROUT1–0 SHOULD BE TIED TOGETHER EXTERNALLY AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. 100µF Figure 6. External Crystal Connections Figure 7. Frequency Modification Methods CLKIN CLKOUT XTAL PLL 0.5 × to 64× ÷1 to 15 ÷ 1, 2,4,8 VCO CLKI N “FI NE” ADJUSTMENT REQUI RES PLL SEQ UENCING “CO ARSE” ADJUSTMENT ON-THE-FLY CCLK SCLK SCLK ≤ CCLK SCLK ≤ 133 MHz |
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