ADSP-BF533SBB500 datasheet(17/60 Pages) AD

Part #	ADSP-BF533SBB500

Description	Blackfin Embedded Processor

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ADSP-BF533

Rev. D

|

Page 17 of 60

|

September 2006

PIN DESCRIPTIONS

ADSP-BF533 processor pin definitions are listed in Table 9.

All pins are three-stated during and immediately after reset,

except the memory interface, asynchronous memory control,

and synchronous memory control pins, which are driven high.

If BR is active, then the memory pins are also three-stated. All

unused I/O pins have their input buffers disabled with the

exception of the pins that need pull-ups or pull-downs as noted

in the table footnotes.

In order to maintain maximum functionality and reduce pack-

age size and pin count, some pins have dual, multiplexed

functionality. In cases where pin functionality is reconfigurable,

the default state is shown in plain text, while alternate function-

ality is shown in italics.

Table 9. Pin Descriptions

Pin Name

Type Function

Driver

Type1

Pull-Up/Down Requirement

Memory Interface

ADDR19–1

O

Address Bus for Async/Sync Access

A

None

DATA15–0

I/O

Data Bus for Async/Sync Access

A

None

ABE1–0/SDQM1–0

O

Byte Enables/Data Masks for Async/Sync Access A

None

BR

I

Bus Request

Pull-up Required If Function Not Used

BG

OBus Grant

A

None

BGH

O

Bus Grant Hang

A

None

Asynchronous Memory Control

AMS3–0

O

Bank Select

A

None

ARDY

I

Hardware Ready Control

Pull-up Required If Function Not Used

AOE

O

Output Enable

A

None

ARE

ORead Enable

A

None

AWE

OWrite Enable

A

None

Synchronous Memory Control

SRAS

O

Row Address Strobe

A

None

SCAS

O

Column Address Strobe

A

None

SWE

OWrite Enable

A

None

SCKE

O

Clock Enable

A

None

CLKOUT

O

Clock Output

B

None

SA10

O

A10 Pin

A

None

SMS

O

Bank Select

A

None

Timers

TMR0

I/O

Timer 0

C

None

TMR1/PPI_FS1

I/O

Timer 1/PPI Frame Sync1

CNone

TMR2/PPI_FS2

I/O

Timer 2/PPI Frame Sync2

CNone

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ADSP-BF533SBB500 Datasheet(PDF) 17 Page - Analog Devices

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