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ADSP-BF533SBBC500 Datasheet(PDF) 33 Page - Analog Devices

Part # ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF533SBBC500 Datasheet(HTML) 33 Page - Analog Devices

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ADSP-BF533
Rev. D
|
Page 33 of 60
|
September 2006
Table 24. Serial Ports—Enable and Three-State
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Switching Characteristics
t
DTENE
Data Enable Delay from External TSCLK1
00ns
t
DDTTE
Data Disable Delay from External TSCLK1
10.0
10.0
ns
t
DTENI
Data Enable Delay from Internal TSCLK1
−2.0
−2.0
ns
t
DDTTI
Data Disable Delay from Internal TSCLK1
3.0
3.0
ns
1 Referenced to drive edge.
Table 25. External Late Frame Sync
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Switching Characteristics
t
DDTLFSE Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0
1, 2
10.0
10.0
ns
t
DTENLFS Data Enable from Late FS or MCE = 1, MFD = 0
1, 2
00
ns
1 MCE = 1, TFS enable and TFS valid follow t
DTENLFS and tDDTLFSE.
2 If external RFS/TFS setup to RSCLK/TSCLK > t
SCLKE/2, then tDDTE
/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.


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