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SST49LF016C-66-4C-WHE Datasheet(PDF) 11 Page - Silicon Storage Technology, Inc |
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SST49LF016C-66-4C-WHE Datasheet(HTML) 11 Page - Silicon Storage Technology, Inc |
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11 / 37 page  Data Sheet 16 Mbit LPC Serial Flash SST49LF016C 11 ©2006 Silicon Storage Technology, Inc. S71237-07-000 9/06 Load Enable The Load Enable pin (LD#), is an input pin which when low, indicates the host is loading data in an AAI programming cycle. Data is loaded in the SST49LF016C at the rising edge of the clock. If LD# is high, it signals the AAI interface that the host is terminating the command. LD# low/high switches the RY/BY# output from buffer free flag to pro- gramming complete flag (see Table 18). No Connection (NC) These pins are not connected internally. DESIGN CONSIDERATIONS SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket. The RST# pin must remain stable at VIH for the entire duration of an Erase operation. WP#/AAI must remain stable at VIH for the entire duration of the Erase and Program operations for non-Boot Block sectors. To write data to the top Boot Block sectors, the TBL# pin must also remain stable at VIH for the entire duration of the Erase and Program operations. MODE SELECTION The SST49LF016C flash memory device operates in two distinct interface modes: the LPC mode and the Auto Address Increment (AAI) mode. The WP#/AAI pin is used to set the interface mode selection. The device is in AAI mode when the WP#/AAI pin is set to the Supervoltage VH (9±0.5V), and in the LPC mode when the WP#/AAI is set to VIL/VIH. The mode selection must be configured prior to device operation. LPC MODE Device Operation The SST49LF016C supports Multi-Byte Firmware Memory Read and Write cycle types as defined in Low Pin Count Interface Specification, Revision 1.1. Table 2 shows the size of transfer supported by the SST49LF016C. The LPC mode uses a 5-signal communication interface: one control line, LFRAME#, which is driven by the host to start or abort a bus cycle, a 4-bit data bus, LAD[3:0], used to communicate cycle type, cycle direction, ID selection, address, data and sync fields. The device enters standby mode when LFRAME# is taken high and no internal opera- tion is in progress. The host drives LFRAME# signal from low-to-high to cap- ture the start field of a LPC cycle. On the cycle in which LFRAME# goes inactive, the last latched value is taken as the START value. The START value determines whether the SST49LF016C will respond to a Firmware Memory Read/Write cycle type as defined in Table 3. See following sections on details of Firmware Memory cycle types (Tables 4 and 5). Two-cycle Program and Erase command sequences are used to initiate Firmware Memory Program and Erase operations. See Table 8 for a listing of Program and Erase commands. TABLE 2: Transfer Size Supported Cycle Type Size of Transfer Firmware Memory Read 1, 2, 4, 16, 128 Bytes Firmware Memory Write 1, 2, 4 Bytes T2.1 1237 TABLE 3: Firmware Memory Cycles START Field Definition START Value Definition 1101 Start of a Firmware Memory Read cycle 1110 Start of a Firmware Memory Write cycle T3.1 1237 |
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