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SST49LF016C Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc |
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SST49LF016C Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc |
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10 / 37 page  10 Data Sheet 16 Mbit LPC Serial Flash SST49LF016C ©2006 Silicon Storage Technology, Inc. S71237-07-000 9/06 Clock The LCLK pin accepts a clock input from the host controller. Input/Output Communications The LAD[3:0] pins are used to serially communicate cycle information such as cycle type, cycle direction, ID selection, address, data, and sync fields. Input Communication Frame The LFRAME# pin is used to indicate start of a LPC bus cycle. The pin is also used to abort an LPC bus cycle in progress. Reset A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, LAD[3:0], in a high impedance state. The reset signal must be held low for a minimum of time TRSTP. A reset latency occurs if a reset pro- cedure is performed during a Program or Erase operation. See Table 25, Reset Timing Parameters, for more informa- tion. A device reset during an active Program or Erase oper- ation will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete Erase or Program operation. Identification Inputs These pins are part of a mechanism that allows multiple devices to be attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:0] = 0; all subsequent devices should use sequential count-up strapping. These pins are internally pulled-down with a resistor between 20-100 KΩ. General Purpose Inputs The General Purpose Inputs (GPI[4:0]) can be used as dig- ital inputs for the CPU to read. The GPI register holds the values on these pins. The data on the GPI pins must be stable before the start of a GPI register Read and remain stable until the Read cycle is complete. The pins must be driven low, VIL, or high, VIH but not left unconnected (float). Write Protect / Top Block Lock The Top Boot Lock (TBL#) and Write Protect (WP#/AAI) pins are provided for hardware write protection of device memory in the SST49LF016C. The TBL# pin is used to write protect 16 KByte at the highest memory address range for the SST49LF016C. WP#/AAI pin write protects the remaining sectors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase opera- tions of the top Boot Block. When TBL# pin is held high, write protection of the top Boot Block is then determined by the Boot Block Locking registers. The WP#/AAI pin serves the same function for the remaining sectors of the device memory. The TBL# and WP#/AAI pins write protection functions operate independently of one another. Both TBL# and WP#/AAI pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or WP#/AAI pin during a Program or Erase operation could cause unpre- dictable results. TBL# and WP#/AAI pins cannot be left unconnected. TBL# is internally OR’ed with the top Boot Block Locking register. When TBL# is low, the top Boot Block is hardware write protected regardless of the state of the Write-Lock bit for the Boot Block Locking register. Clearing the Write-Pro- tect bit in the register when TBL# is low will have no func- tional effect, even though the register may indicate that the block is no longer locked. WP#/AAI is internally OR’ed with the Block Locking regis- ter. When WP#/AAI is low, the blocks are hardware write protected regardless of the state of the Write-Lock bit for the corresponding Block Locking registers. Clearing the Write-Protect bit in any register when WP#/AAI is low will have no functional effect, even though the register may indi- cate that the block is no longer locked. AAI Enable The AAI Enable pin (WP#/AAI) is used to enable the Auto Address Increment (AAI) mode. When the WP#/AAI pin is set to the Supervoltage VH (9±0.5V), the device is in AAI mode with Multi-Byte programming. When the WP#/AAI pin is brought to VIL/VIH levels, the device returns to LPC mode. Ready/Busy The Ready/Busy pin (RY/BY#), is an open drain output which indicates the device is ready to accept data in an AAI mode, or that the internal programming cycle is complete. The pin is used in conjunction with the LD# pin to switch between these two flag states (see Table 18). |
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