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SST49LF016C Datasheet(PDF) 9 Page - Silicon Storage Technology, Inc |
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SST49LF016C Datasheet(HTML) 9 Page - Silicon Storage Technology, Inc |
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9 / 37 page  Data Sheet 16 Mbit LPC Serial Flash SST49LF016C 9 ©2006 Silicon Storage Technology, Inc. S71237-07-000 9/06 PIN DESCRIPTIONS TABLE 1: Pin Description Symbol Pin Name Type1 1. I=Input, O=Output Interface Functions AAI LPC LCLK Clock I X X To accept a clock input from the control unit LAD[3:0] Address and Data I/O X X To provide LPC bus information, such as addresses and command Inputs/ Outputs data. LFRAME# Frame I X X To indicate the start of a data transfer operation; also used to abort an LPC cycle in progress. RST# Reset I X X To reset the operation of the device INIT# Initialize I X X This is the second reset pin for in-system use. This pin is internally combined with the RST# pin. If this pin or RST# pin is driven low, identical operation is exhibited. ID[3:0] Identification Inputs I X X These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:0]=0000, all subsequent devices should use sequential up-count strapping. These pins are inter- nally pulled-down with a resistor between 20-100 K Ω. When in AAI mode, these pins operate identically as in Firmware Memory cycles. GPI[4:0] General Purpose Inputs I X These individual inputs can be used for additional board flexibility. The state of these pins can be read through LPC registers. These inputs should be at their desired state before the start of the LPC clock cycle dur- ing which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated. GPI[2:4] are ignored when in AAI mode. TBL# Top Block Lock I X When low, prevents programming to the boot block sectors at top of device memory. When TBL# is high it disables hardware write protection for the top block sectors. This pin cannot be left unconnected. TBL# setting is ignored when in AAI mode. WP#/AAI Write Protect I X When low, prevents programming to all but the highest addressable block (Boot Block). When WP# is high it disables hardware write protection for these blocks. This pin cannot be left unconnected. WP#/AAI AAI Enable I X When set to the Supervoltage VH = 9V, configures the device to program multiple bytes in AAI mode. When brought to VIL/VIH, returns device to LPC mode. RY/BY# Ready/Busy# O X Open drain output that indicates the device is ready to accept data in an AAI mode, or that the internal cycle is complete. Used in conjunction with LD# pin to switch between these two flag states. LD# Load-Enable# I X Input pin which when low, indicates the host is loading data in an AAI pro- gramming cycle. If LD# is high, the host signals the AAI interface that it is terminating a command. LD# low/high switches the RY/BY# output from a “buffer free” flag to a “programming complete” flag. VDD Power Supply PWR X X To provide power supply (3.0-3.6V) VSS Ground PWR X X Circuit ground (0V reference) NC No Connection N/A N/A Unconnected pins. T1.2 1237 |
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