ZL50063 datasheet(33/60 Pages) ZARLINK

Part #	ZL50063

Description	16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output

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Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

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ZL50063

Data Sheet

33

Zarlink Semiconductor Inc.

10

FBDEN

0

Frame Boundary Discriminator Enable

When LOW, the frame boundary discriminator function is disabled.

When HIGH, enables frame boundary discriminator function which allows the

device to tolerate inconsistent frame boundaries, hence improving the tolerance to

cycle-to-cycle variation on the input clock.

9

Reserved

0

Reserved

Must be set to 0 for normal operation

8FPW

0

Frame Pulse Width

When LOW, the user must apply a 122ns frame pulse on FP8i; the FP8o pin will

output a 122ns wide frame pulse; FP16o will output a 61ns wide frame pulse.

When HIGH, the user must apply a 244ns frame pulse on FP8i; the FP8o pin will

output a 244ns wide frame pulse; FP16o will output a 122ns wide frame pulse.

7

Reserved

0

Reserved

Must be set to 0 for normal operation

6C8IPOL

0

8MHz Input Clock Polarity

The frame boundary is aligned to the falling or rising edge of the input clock.

When LOW, the frame boundary is aligned to the clock falling edge.

When HIGH, the frame boundary is aligned to the clock rising edge.

5

COPOL

0

Output Clock Polarity

When LOW, the output clock has the same polarity as the input clock.

When HIGH, the output clock is inverted.

This applies to both the 8MHz (C8o) and 16MHz (C16o) output clocks.

4MBP

0

Memory Block Programming

When LOW, the memory block programming mode is disabled.

When HIGH, the connection memory block programming mode is ready to program

the Local Connection Memory (LCM) and the Backplane Connection Memory

(BCM).

3OSB

0

Output Stand By

This bit enables the BSTo0-15 and LSTo0-15 serial outputs.

When LOW, BSTo0-15 and LSTo0-15 are driven HIGH or high impedance,

dependent on the BORS and LORS pin settings respectively.

When HIGH, BSTo0-15 and LSTo0-15 are enabled.

2

Reserved

0

Reserved

Must be set to 0 for normal operation

1:0

MS[1:0]

0

Memory Select Bits

These three bits select the connection or data memory for subsequent microport

memory access operations:

00 selects Local Connection Memory (LCM) for read or write operations.

01 selects Backplane Connection Memory (BCM) for read or write operations.

10 selects Local Data Memory (LDM) for read-only operation.

11 selects Backplane Data Memory (BDM) for read-only operation.

Bit

Name

Reset

Value

Description

Table 11 - Control Register Bits (continued)

Output Control with ODE pin and OSB bit

ODE Pin

OSB bit

BSTo0-15, LSTo0-15

0X

Disabled

10

Disabled

1

Enabled

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