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ZL50063 Datasheet(PDF) 32 Page - Zarlink Semiconductor Inc

Part No. ZL50063
Description  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output
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Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
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ZL50063 Datasheet(HTML) 32 Page - Zarlink Semiconductor Inc

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ZL50063
Data Sheet
32
Zarlink Semiconductor Inc.
12.0
Internal Register Mappings
When the most significant bit, A14, of the address bus is set to ’0’, the microprocessor is performing an access to
one of the device’s internal registers. Address bits A13-A0 indicate which particular register is being accessed.
13.0
Detailed Register Descriptions
This section describes the registers that are used in the device.
13.1
Control Register (CR)
Address 0000H.
The Control Register defines which memory is to be accessed. It initiates the memory block programming mode
and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows:
A14-A0
Register
0000H
Control Register, CR
0001H
Block Programming Register, BPR
0023H - 0032H
Local Input Bit Delay Register 0 - 15, LIDR0 - 15
0063H - 0072H
Backplane Input Bit Delay Register 0 - 15, BIDR0 - 15
0083H - 0092H
Local Output Advancement Register 0 - 15, LOAR0 - 15
00A3H - 00B2H
Backplane Output Advancement Register 0 - 15, BOAR0 - 15
014DH
Memory BIST Register, MBISTR
3FFFH
Device Identification Register, DIR
Table 10 - Address Map for Registers (A14 = 0)
Bit
Name
Reset
Value
Description
15:13
FBD_
MODE[2:0]
0
Frame Boundary Discriminator Mode
When set to 111B, the Frame Boundary Discriminator can handle both low
frequency and high frequency jitter.
When set to 000B, the Frame Boundary Discriminator is set to handle lower
frequency jitter only.
All other values are reserved.
These bits are ignored when FBDEN bit is LOW.
12
SMPL_
MODE
0
Sample Point Mode
When LOW the input bit sampling point is always at the 3/4 bit location. The input bit
fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value
of the LIDR0 to LIDR15 and BIDR0 to BIDR15 registers.
When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit
location as per the value of the LIDR0 to LIDR15 and BIDR0 to BIDR15 registers. In
addition the incoming data can be delayed by 0 to 7 bits in 1 bit increments.
See Table 13, Table 14, Table 15 and Table 16 for details.
11
Reserved
0
Reserved
Must be set to 0 for normal operation
Table 11 - Control Register Bits


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