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ZL50063 Datasheet(PDF) 18 Page - Zarlink Semiconductor Inc

Part No. ZL50063
Description  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output
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Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
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ZL50063 Datasheet(HTML) 18 Page - Zarlink Semiconductor Inc

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ZL50063
Data Sheet
18
Zarlink Semiconductor Inc.
2.3
Input Frame Pulse and Generated Frame Pulse Alignment
The ZL50063 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are
aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to
the output of the device such that data which is input during Frame N is output during Frame N+2.
For further details of frame pulse conditions and options, see Section 13.1, Control Register (CR), Figure 15, Frame
Boundary Conditions, ST-BUS Operation, and Figure 16, Frame Boundary Conditions, GCI-Bus Operation.
Figure 7 - Input and Output (Generated) Frame Pulse Alignment for Different Data Rates
The tFBOS is the offset between the input frame pulse, FP8i, and the generated output frame pulse, FP8o. Refer to
the “AC Electrical Characteristics,” on page 47. Note that although the figure above shows the traditional setups of
the frame pulses and clocks for both ST-BUS and GCI-Bus configurations, the devices can be configured to
accept/generate double-width frame pulses (if the FPW bit in the Control Register is set) as well as to use the
opposite clock edge for frame-boundary determination (using the C8IPOL and COPOL bits in the Control Register).
See the timing diagrams in “AC Electrical Characteristics,” on page 47 for all of the available configurations.
2.4
Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
To improve the jitter tolerance of the ZL50063, a Frame Boundary Discriminator (FBD) circuit was added to the
device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled.
The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits
FBD_MODE[2:0] are set to 000B, the FBD is set to handle lower frequency jitter only (<8kHz). When bits
FBD_MODE[2:0] are set to 111B, the FBD can handle both low frequency and high frequency jitter. All other values
are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set
HIGH, bits FBD_MODE[2:0] should be set to 111B to improve the high frequency jitter handling capability.
To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be
optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by
programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused
by jitter. There are, however, some cases where data experience more delay than the timing signals. A common
example is when multiple data lines are tied together to form bidirectional buses. The large bus loading may cause
data to be delayed. If this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. The optimum
sampling point is dependent on the application. The user should optimize the sampling point to achieve the best
jitter tolerance performance.
C8o
FP8o
FP8i
C8i
tFBOS
BSTo/LSTo0-15
(32Mbps)
CH
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 1516 1718 19 20
21 22 23 24 25 26 272829 30 31 32 33 34 35 36 3738 39 40 41 42 43 44
45 46 47
BSTi/LSTi0-15
(32Mbps)
CH
0
1
2
3
4
5
6
7
8
9 10
11 121314 15 16 17 18 19 20
21 22 23 24 25 26 27 28 2930 31 3233 34 3536 37 38 3940 41 4243 44 45 4647


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