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ZL50063 Datasheet(PDF) 9 Page - Zarlink Semiconductor Inc

Part No. ZL50063
Description  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output
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Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
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ZL50063 Datasheet(HTML) 9 Page - Zarlink Semiconductor Inc

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ZL50063
Data Sheet
9
Zarlink Semiconductor Inc.
Pin Description
Pin Name
ZL50063
Package
Coordinates
(196-ball
PBGA)
Description
Device Timing
C8i
P10
Master Clock (5V Tolerant Schmitt-Triggered Input). This pin accepts an
8.192MHz clock. The internal frame boundary is aligned with the clock falling
or rising edge, as controlled by the C8IPOL bit in the Control Register. Input
data on both the Backplane and Local sides (BSTi0-15 and LSTi0-15) must
be aligned to this clock and the accompanying input frame pulse, FP8i.
FP8i
M10
Frame Pulse Input (5V Tolerant Schmitt-Triggered Input). When the
Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this
pin accepts a 122ns-wide frame pulse. When the FPW bit is HIGH, this pin
accepts a 244ns-wide frame pulse. The device will automatically detect
whether an ST-BUS or GCI-Bus style frame pulse is applied. Input data on
both the Backplane and Local sides (BSTi0-15 and LSTi0-15) must be
aligned to this frame pulse and the accompanying input clock, C8i.
C8o
N10
C8o Output Clock (5V Tolerant Three-state Output). This pin outputs an
8.192MHz clock generated within the device. The clock falling edge or rising
edge is aligned with the output frame boundary presented on FP8o; this edge
polarity alignment is controlled by the COPOL bit of the Control Register.
Output data on both the Backplane and Local sides (BSTo0-15 and
LSTo0-15) will be aligned to this clock and the accompanying output frame
pulse, FP8o.
FP8o
N11
Frame Pulse Output (5V Tolerant Three-state Output). When the Frame
Pulse Width bit (FPW) of the Control Register is LOW (default), this pin
outputs a 122ns-wide frame pulse. When the FPW bit is HIGH, this pin
outputs a 244ns-wide frame pulse. The frame pulse, running at 8kHz rate, will
have the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i).
Output data on both the Backplane and Local sides (BSTo0-15 and
LSTo0-15) will be aligned to this frame pulse and the accompanying output
clock, C8o.
C16o
M9
C16o Output Clock (5V Tolerant Three-state Output). This pin outputs a
16.384MHz clock generated within the device. The clock falling edge or rising
edge is aligned with the output frame boundary presented on FP16o; this
edge polarity alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides (BSTo0-15 and
LSTo0-15) will be aligned to this clock and the accompanying output frame
pulse, FP16o.
FP16o
P12
Frame Pulse Output (5V Tolerant Three-state Output). When the Frame
Pulse Width bit (FPW) of the Control Register is LOW (default), this pin
outputs a 61ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs
a 122ns-wide frame pulse. The frame pulse, running at 8kHz rate, will have
the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i).
Output data on both the Backplane and Local sides (BSTo0-15 and
LSTo0-15) will be aligned to this frame pulse and the accompanying output
clock, C16o.


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