ZL50063 datasheet(36/60 Pages) ZARLINK

Part #	ZL50063

Description	16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output

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Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

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ZL50063

Data Sheet

36

Zarlink Semiconductor Inc.

13.2

Block Programming Register (BPR)

Address 0001H.

The Block Programming Register stores the bit patterns to be loaded into the connection memories when the

Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the BPR register must

be defined in the same write operation.

The BPE bit is set HIGH to commence the block programming operation. Programming is completed in one frame

period and may be initiated at any time within a frame. The BPE bit returns to LOW to indicate that the block

programming function has completed.

When BPE is HIGH, no other bits of the BPR register may be changed for at least a single frame period, except to

abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the

Control Register bit, MBP, to LOW.

The BPR register is configured as follows.

.

Table 12 - Block Programming Register Bits

Bit

Name

Reset

Value

Description

15:7

Reserved

0

Reserved

Must be set to 0 for normal operation

6:4

BBPD[2:0]

0

Backplane Block Programming Data

These bits refer to the value loaded into the Backplane Connection Memory

(BCM) when the Memory Block Programming feature is activated.

When the MBP bit in the Control Register (CR) is set HIGH and BPE (in this

register) is set HIGH, the contents of bits BBPD[2:0] are loaded into bits 15-13,

respectively, of the BCM. Bits 12-0 of the BCM are set LOW.

3:1

LBPD[2:0]

0

Local Block Programming Data

These bits refer to the value loaded into the Local Connection Memory (LCM),

when the Memory Block Programming feature is activated.

When the MBP bit in the Control Register is set HIGH and BPE (in this register)

is set HIGH, the contents of bits LBPD[2:0] are loaded into bits 15-13,

respectively, of the LCM. Bits 12-0 of the LCM are set LOW.

0BPE

0

Block Programming Enable

A LOW to HIGH transition of this bit enables the Memory Block Programming

function. A LOW will be returned after 125

µs, upon completion of programming.

Set LOW to abort the programming operation.

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