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ZL50052 Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc

Part No. ZL50052
Description  8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
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Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
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ZL50052 Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc

 
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ZL50052
Data Sheet
3
Zarlink Semiconductor Inc.
Device Overview
The ZL50052 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports operate at
32.768 Mbps.
The ZL50052 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
Input-to-Output Unidirectional, supporting 8 K x 8 K switching
Backplane-to-Local Bi-directional, supporting 4 K x 4 K data switching
Local-to-Backplane Bi-directional, supporting 4 K x 4 K data switching
Backplane-to-Backplane Bi-directional, supporting 4 K x 4 K data switching
Local-to-Local Bi-directional, supporting 4 K x 4 K data switching
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
In Connection Mode, the contents of the connection memory define, for each output stream and channel, the
source stream and channel, (stored in data memory), to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per-channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing
for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-
Bus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period, the input frame pulse format is determined before
switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of
the Backplane and Local ports.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and four
control signals. The microprocessor may monitor channel data in the Backplane and Local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The ZL50052 is available in one package:
a 15 mm x 15 mm body, 1 mm ball-pitch, 196-PBGA


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