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ZL50052 Datasheet(PDF) 11 Page - Zarlink Semiconductor Inc

Part # ZL50052
Description  8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

ZL50052 Datasheet(HTML) 11 Page - Zarlink Semiconductor Inc

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ZL50052
Data Sheet
11
Zarlink Semiconductor Inc.
LORS
H13
Local Output Reset State (5 V Tolerant Input with Internal Pull-down)
When this input is LOW, the device will initialize with the LSTo0-7 outputs
driven high. Following initialization, the Local stream outputs are always
active.
When this input is HIGH, the device will initialize with the LSTo0-7 outputs at
high impedance. Following initialization, the Local stream outputs may be set
active or high impedance using the ODE pin or on a per-channel basis with
the LE bit in the Local Connection Memory.
LSTo0-7
B13, B14, D14,
C14, D12, E14,
D13, E13
Local Serial Output Streams 0 to 7 (5 V Tolerant Three-state Outputs
with Slew-Rate Control)
These pins output serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
Refer to the descriptions of the LORS and ODE pins for control of the output
HIGH or high impedance state.
Microprocessor Port Signals
A0 - A14
B1, B4, B5, D5,
A3, A4, C6, B6,
A5, A6, C7, B7,
A7, A8, B8
Address 0 - 14 (5 V Tolerant Inputs)
These pins form the 15-bit address bus to the internal memories and
registers.
A0 = LSB
D0 - D15
N7, P7, P6, N6,
P5, M6, P4, N5,
P3, P2, N3, N4,
M5, N2, M4, M3
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with Slew-Rate Control)
These pins form the 16-bit data bus of the microprocessor port.
D0 = LSB
CS
A10
Chip Select (5 V Tolerant Input)
Active LOW input used by the microprocessor to enable the microprocessor
port access
Note that a minimum of 30 ns must separate the de-assertion of DTA (to
high) and the assertion of CS and/or DS to initiate the next access.
DS
C8
Data Strobe (5 V Tolerant Input)
This active LOW input works in conjunction with CS to enable the
microprocessor port read and write operations.
Note that a minimum of 30 ns must separate the de-assertion of DTA (to
high) and the assertion of CS and/or DS to initiate the next access.
R/W
A9
Read/Write (5 V Tolerant Input)
This input controls the direction of the data bus lines (D0-D15) during a
microprocessor access.
DTA
D9
Data Transfer Acknowledgment (5 V Tolerant Three-state Output)
This active LOW output indicates that a data bus transfer is complete. A
pull-up resistor is required to hold a HIGH level.
Note that a minimum of 30 ns must separate the de-assertion of DTA (to
high) and the assertion of CS and/or DS to initiate the next access.
Pin Description (continued)
Pin Name
ZL50052
Package
Coordinates
(196 ball
PBGA)
Description


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