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ZL50052 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc

Part No. ZL50052
Description  8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
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Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
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ZL50052 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc

 
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
8,192 channel x 8,192 channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to form
a non-blocking switching matrix with 16 input
streams and 16 output streams
4,096 channel x 4,096 channel non-blocking
Backplane input to Local output stream switch
4,096 channel x 4,096 channel non-blocking
Local input to Backplane output stream switch
4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
4,096 channel x 4,096 channel non-blocking
Local input to Local output stream switch
Backplane port accepts 8 input and 8 output ST-
BUS streams with data rate of 32.768 Mbps
Local port accepts 8 input and 8 output ST-BUS
streams with data rate of 32.768 Mbps
Exceptional input clock jitter tolerance (14 ns)
Per-stream bit delay for Local and Backplane
input streams
Per-stream advancement for Local and
Backplane output streams
Constant 2-frame throughput delay for frame
integrity
Per-channel high impedance output control for
Local and Backplane streams
Per-channel driven-high output control for Local
and Backplane streams
Per-channel message mode for Local and
Backplane output streams
Connection memory block programming for fast
device initialization
Automatic selection between ST-BUS and GCI-
Bus operation
Non-multiplexed Motorola microprocessor
interface
December 2003
Ordering Information
ZL50052GAC
196 ball PBGA
-40
°C to +85°C
ZL50052
8 K Channel Digital Switch with High Jitter
Tolerance, Single Rate (32 Mbps),
and 16 Inputs and 16 Outputs
Data Sheet
Figure 1 - ZL50052 Functional Block Diagram
Backplane Data Memories
(4,096 channels)
DS CS R/W
A14-0
DTA
D15-0
Test Port
Microprocessor Interface
and Internal Registers
VSS (GND)
VDD_CORE
TDi TDo TCK TRST
TMS
LSTo0-7
(4,096 locations)
RESET
Local
Interface
Connection Memory
BSTi0-7
Input
Timing Unit
FP8i
PLL
LSTi0-7
Interface
Backplane
BSTo0-7
Local
C8i
VDD_IO
ODE
C8o
C16o
FP8o
FP16o
VDD_PLL
Output
Timing
Unit
(4,096 locations)
Connection Memory
Backplane
Interface
Local
Local Data Memories
(4,096 channels)
BORS
LORS


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