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ZL50021 Datasheet(PDF) 63 Page - Zarlink Semiconductor Inc |
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ZL50021 Datasheet(HTML) 63 Page - Zarlink Semiconductor Inc |
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63 / 136 page  ZL50021 Data Sheet 63 Zarlink Semiconductor Inc. Bit Name Description 15 - 11 Unused Reserved. In normal functional mode, these bits MUST be set to zero. 10 FP19EN 19.44 MHz Frame Pulse Output Enable. (For FPo_OFF2 only) This bit is a reserved bit for FPo_OFF0 and FPo_OFF1, and MUST be set to zero. When this bit is high, FPo_OFF2 is negative frame pulse output corresponding to 19.44 MHz without channel offset. When this bit is low, FPo_OFF2 is output frame pulse with channel offset. 9 - 2 FOF[n]OFF7 - 0 FPo_OFF[n] Channel Offset The binary value of these bits refers to the channel offset from original frame bound- ary. Permitted channel offset values depend on bits 1-0 of this register. 1 - 0 FOF[n]C1 - 0 FPo_OFF[n] Control bits Note: [n] denotes output offset frame pulse from 0 to 2. Table 23 - FPo_OFF[n] Register (FPo_OFF[n]) Bits External Read/Write Address: 0005H - 0007H Reset Value: 0000H 15 14 13 12 11 10 9876543210 00 000 FP19 EN FOF[n] OFF7 FOF[n] OFF6 FOF[n] OFF5 FOF[n] OFF4 FOF[n] OFF3 FOF[n] OFF2 FOF[n] OFF1 FOF[n] OFF0 FOF[n] C1 FOF[n] C0 FOF[n]C 1-0 Data Rate (Mbps) FPo_OFF[n] Pulse Cycle Width FOF[n]OFF7 - 0 Permitted Channel Offset Polarity Control Position Control 00 2.048 one 4.096 MHz clock 0 - 31 FPO0P FPO0POS 01 4.096 one 8.192 MHz clock 0 - 63 FPO1P FPO1POS 10 8.192 one 16.384 MHz clock 0 - 127 FPO2P FPO2POS 11 16.384 one 16.384 MHz clock 0 - 255 FPO2P FPO2POS |
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