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ZL50021_0611 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc

Part No. ZL50021_0611
Description  Enhanced 4 K Digital Switch with Stratum 3 DPLL
Download  136 Pages
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Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
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ZL50021_0611 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc

 
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• 4096-channel x 4096-channel non-blocking digital
Time Division Multiplex (TDM) switch at 8.192
and 16.384 Mbps or using a combination of ports
running at 2.048, 4.096, 8.192 and/or
16.384 Mbps
• 32 serial TDM input, 32 serial TDM output
streams
• Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 3
specifications
• Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
• DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
• Programmable key DPLL parameters (filter corner
frequency, locking range, auto-holdover
hysteresis range, phase slope, lock detector
range)
• Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
• Output streams can be configured as bi-
directional for connection to backplanes
November 2006
Ordering Information
ZL50021GAC
256 Ball PBGA
Trays
ZL50021QCC
256 Lead LQFP
Trays
ZL50021QCG1
256 Lead LQFP*
Trays, Bake &
Drypack
ZL50021GAG2
256 Ball PBGA**
Trays, Bake &
Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40
°C to +85°C
ZL50021
Enhanced 4 K Digital Switch with
Stratum 3 DPLL
Data Sheet
Figure 1 - ZL50021 Functional Block Diagram
Data Memory
Internal Registers &
Microprocessor Interface
Output HiZ
Test Port
Control
OSC
DPLL
S/P Converter
STOHZ[15:0]
FPo[3:0]
CKo[5:0]
STio[31:0]
REF0
Connection Memory
Output Timing
STi[31:0]
REF1
REF2
REF3
FPo_OFF[2:0]
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
P/S Converter
OSC_EN
Input Timing
FPi
CKi
MODE_4M0
MODE_4M1
ODE
RESET
VSS
VDD_IO
VDD_CORE
VDD_IOA
VDD_COREA
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08


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