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ZL50020 Datasheet(PDF) 17 Page - Zarlink Semiconductor Inc |
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ZL50020 Datasheet(HTML) 17 Page - Zarlink Semiconductor Inc |
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17 / 83 page  ZL50020 Data Sheet 17 Zarlink Semiconductor Inc. input streams were operating at 16.384 Mbps (256 channels per stream), this would result in 8192 channels. Memory limitations prevent the device from operating at this capacity. A maximum capacity of 2048 channels will occur if eight of the streams are operating at 16.384 Mbps, half of the streams are operating at 8.192 Mbps or all streams operating at 4.096 Mbps. With all streams operating at 2.048 Mbps, the capacity will be reduced to 1024 channels. However, as each stream can be programmed to a different data rate, any combination of data rates can be achieved, as long as the total channel count does not exceed 2048 channels. It should be noted that only full stream can be programmed for use. The device does not allow fractional streams. External High Impedance Control, STOHZ0 - 15. There are 16 external high impedance control signals, STOHZ0 - 15, that are used to control the external drivers for per-channel high impedance operations. Only the first sixteen ST-BUS/GCI-Bus (STio0 - 15) outputs are provided with corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot channels based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin is high and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 15 are enabled. When the ODE pin, OSB (bit 2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 15 are driven high, together with all the ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any unused ST-BUS/GCI-Bus channel (high impedance) are driven high. Refer to Figure 16 on page 28 for a diagrammatical explanation. 4.1 Input Clock (CKi) and Input Frame Pulse (FPi) Timing The frequency of the input clock (CKi) for the ZL50020 depends on the operation mode selected. In divided clock mode, CKi must be at least twice the highest input or output data rate. For example, if the highest input data rate is 4.096 Mbps and the highest output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz, which is twice the highest overall data rate. The only exception to this is for 16.384 Mbps input or output data. In this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. In multiplied clock mode the frequency of CKi must be at least twice the highest input data rate regardless of the output data rate. An APLL is used to multiple CKi to generate an internal clock that is used to output clocks and STio streams. Following the example above, if the highest input data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz, regardless of the output data rate. The only exception to this is for 16.384 Mbps input or output data. In this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. In either mode the user has to program the CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) to indicate the width of the input frame pulse and the frequency of the input clock supplied to the device. l Highest Input or Output Data Rate CKIN 1-0 Bits Input Clock Rate (CKi) Input Frame Pulse (FPi) 8.192 Mbps or 16.384 Mbps 00 16.384 MHz 8 kHz (61 ns wide pulse) 4.096 Mbps 01 8.192 MHz 8 kHz (122 ns wide pulse) 2.048 Mbps 10 4.096 MHz 8 kHz (244 ns wide pulse) Table 1 - CKi and FPi Configurations for Divided Clock Modes Highest Input Data Rate CKIN 1-0 Bits Input Clock Rate (CKi) Input Frame Pulse (FPi) 8.192 Mbps or 16.384 Mbps 00 16.384 MHz 8 kHz (61 ns wide pulse) 4.096 Mbps 01 8.192 MHz 8 kHz (122 ns wide pulse) 2.048 Mbps 10 4.096 MHz 8 kHz (244 ns wide pulse) Table 2 - CKi and FPi Configurations for Multiplied Clock Mode |
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