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ZL50018 Datasheet(PDF) 42 Page - Zarlink Semiconductor Inc |
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ZL50018 Datasheet(HTML) 42 Page - Zarlink Semiconductor Inc |
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42 / 136 page  ZL50018 Data Sheet 42 Zarlink Semiconductor Inc. With a preferred reference, if more than two references are required, or the two references are not in consecutive order, or the roles of the two references need to be interchanged, then external software is required to manually control the reference switching of the DPLL (by monitoring the reference failure status and reprogramming the device accordingly). 12.1.4 Freerun Mode In freerun mode, the DPLL generates a fixed output frequency based on the crystal oscillator and a programmed centre frequency. To meet Stratum 3, the accuracy of the circuitry for the freerunning output clock must be 4.6 ppm or better. The circuit’s freerun accuracy is better than 0.003 ppm. In freerun mode, the DPLL does not lock to any reference. It is important that the device is not simultaneously in freerun mode (see the RCCR Register) and fast lock mode (see the BWCR Register). Otherwise, the output frame pulse may not be generated correctly. 12.1.5 Software Controlled Mode When the DPLL is in the freerun mode, it can be put into software controlled mode by enabling the SWE (bit 3) in the DPLL Control Register (DPLLCR). The Software Delta Frequency Register (SWDFR) contains the frequency offset to which the DPLL outputs will move. If SWF (bit 4) in the DPLL Control Register (DPLLCR) is low, the DPLL outputs will gradually move to the given frequency offset, with the speed defined by the DPLL internal filter and phase alignment speed (phase slope) limiter. If SWF (bit 4) is high, the DPLL outputs will reach the Software Delta Frequency Register (SWDFR) frequency offset immediately after it is written, allowing an external software-based filter and phase alignment speed (phase slope) limiter to be used. When SWE (bit 3) is low or the DPLL is not in the freerun mode, the value of Software Delta Frequency Register (SWDFR) will be ignored. For detailed description of the DPLL Control Register (DPLLCR) bits and the Software Delta Frequency Register (SWDFR) bits see Table 29 on page 65, and Table 33 on page 70, respectively. 12.1.6 DPLL Internal Reset Mode DPLL_IRM (bit 0) in the DPLL Control Register (DPLLCR) enables the internal reset mode. In the internal reset mode, the DPLL module is disabled to save power. The circuit will be reset continuously and no output clocks will be generated. When the internal DPLL module is in the internal reset mode, all registers remain accessible. Note that applying the DPLL reset does not reset the DPLL registers: they preserve the values that they had prior to entering reset. 13.0 DPLL Frequency Behaviour 13.1 Input Frequencies The DPLL is capable of synchronizing to one of the following input frequencies: 8kHz 1.544 MHz (DS1) 2.048 MHz (E1) 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Table 9 - DPLL Input Reference Frequencies |
Similar Part No. - ZL50018_06 |
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Similar Description - ZL50018_06 |
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