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ZL50015 Datasheet(PDF) 67 Page - Zarlink Semiconductor Inc

Part # ZL50015
Description  Enhanced 1 K Digital Switch with Stratum 4E DPLL
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

ZL50015 Datasheet(HTML) 67 Page - Zarlink Semiconductor Inc

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ZL50015
Data Sheet
67
Zarlink Semiconductor Inc.
Bit
Name
Description
15
Unused
Reserved. In normal functional mode, this bit is zero.
14 - 0
FOF14 - 0
Frequency Offset Bits: The binary value of these bits represents the current deviation
of the DPLL output from its center frequency. Defined in same units as CFN in the 2's
complement format.
Note 1: Output frequency offset, relative to master clock, will be represented as the following:
+10 ppm: CFN x 0.00001 = 440 = 01B8H
-10 ppm: CFN x (-0.00001) = -440 = 7E48H
Table 30 - Frequency Offset Register (FOR) Bits - Read Only
External Read Only Address: 0045H
15
14
13
12
11
10
98
7654
321
0
0FOF
14
FOF
13
FOF
12
FOF
11
FOF
10
FOF
9
FOF
8
FOF
7
FOF
6
FOF
5
FOF
4
FOF
3
FOF
2
FOF
1
FOF
0


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