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ZL50010 Datasheet(PDF) 26 Page - Zarlink Semiconductor Inc |
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ZL50010 Datasheet(HTML) 26 Page - Zarlink Semiconductor Inc |
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26 / 87 page  ZL50010 Data Sheet 26 Zarlink Semiconductor Inc. 2.3.7 External High Impedance Control, STOHZ 0 to 15 The STOHZ 0 to 15 outputs are provided to control the external tristate ST-BUS drivers for per-channel high impedance operations. The STOHZ outputs are sent out in 32, 64 or 128 timeslots corresponding to the output channels for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps output streams respectively. Each control timeslot lasts for one channel time. When the ODE pin is high, the STOHZ 0 - 15 are enabled. When the ODE pin or the RESET pin is low, the STOHZ 0 - 15 are driven high. STOHZ outputs are also driven high if their corresponding ST-BUS outputs are not in use. Figure 20 gives an example when channel 2 of a given ST-BUS output is programmed in the high impedance state, the corresponding STOHZ pin drives high for one channel time at the channel 2 timeslot. By default, the output timing of the STOHZ signals follow the same timing as their corresponding STo signals including any user-programmed channel and bit delay and fractional bit advancement. In addition, the device allows users to advance the STOHZ signals from their default positions to a maximum of four 15.2 ns steps (or four 1/4 bit steps) using Bit 3 to 5 of the Stream Output Control Register (SOCR). Bit 6 in the Stream Output Control Register selects the step resolution as 15.2 ns or 1/4 data bit. The additional advancement feature allows the STOHZ signals to better match the high impedance timing required by the external ST-BUS drivers. When the device is in DPLL Master mode (or Freerun mode) and the additional STOHZ advancement is set to zero, there is no phase difference between the STo0 - 15 and the STOHZ 0 to 15. When the device is in DPLL Master mode (or Freerun mode) and the additional STOHZ advance is not zero, the phase correction of 6.25 ns could happen between the STo0 - 15 and STOHZ 0 to 15 because these outputs are clocked by various internal clock edges and the DPLL output has the intrinsic jitter of 6.25 ns. When the device is in the DPLL Bypass Mode, there is no phase correction between the STo0 -15 of the STOHZ 0- 15 regardless whether the additional STOHZ advancement is enabled or disabled. Figure 20 - Example: External High Impedance Control Timing Output Frame Boundary Ch1 Ch0 SToY Ch3 Ch2 Last Ch Last Ch Last Ch-1 Last Ch -2 Ch0 FPo HiZ STOHZ Y Note: Last Channel = 31, 63, 127 for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps mode respectively STOHZ Y Note: Y = 0 to 15 STOHZ Advancement (Programmable in 4 steps of 15.2 ns or 1/4 bit) (Default = No Adv.) (With Adv.) |
Similar Part No. - ZL50010_06 |
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Similar Description - ZL50010_06 |
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