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MODE Selection Pins for Both Packages

Package Heat Dissipation Ratings

(1)

TAS5162

SLES194B – OCTOBER 2006 – REVISED MARCH 2007

GENERAL INFORMATION (continued)

MODE PINS

PWM INPUT

OUTPUT CONFIGURATION

PROTECTION SCHEME

M3

M2

M1

0

0

0

2 channels BTL output

0

0

1

2 channels BTL output

0

1

0

2 channels BTL output

0

1

1

1 channel PBTL output

PBTL mode, full protection. Only PWM_A input

is used.

difference in SE mode is that OUT_X is Hi-Z

1

0

0

4 channels SE output

instead of a pulldown through internal pulldown

resistor.

1

0

1

4 channels SE output - No

(1,0,0); however, the PWM input protection is

PWM Input protection, latching

disabled. Also, overcurrent detection will latch if

shutdown

an error occurs.

1

1

0

Reserved

1

1

1

(1)

The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific

mode.

(2)

An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors

like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.

PARAMETER

TAS5162DKD

TAS5162DDV

1.0

1.1

1.5

2.2

5.0

7.4

(1)

JC is junction-to-case, CH is case-to-heatsink.

(2)

3

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